The present disclosure relates to time difference adjustment circuits for adjusting the time difference between edges of two input signals and time-to-digital converters including the same.
In recent years, the operating voltage of LSIs has been reduced due to reduction in size of the LSIs. Therefore, it has become difficult to increase the SN ratio of signals in signal processing along a voltage direction. For this reason, the analog quantity along a time axis direction, that is, time difference information has to be used to perform the signal processing, and in recent years, time-to-digital converters for performing digital conversion of the time difference information have been and are being developed.
In general, a time-to-digital converter includes a time difference adjustment circuit for adjusting the time difference between edges of two input signals. Specifically, the time difference adjustment circuit delays one of the two input signals by using a delay circuit to adjust the time difference between the edges of the two input signals. As a delay circuit, an inverter chain including a plurality of cascade-connected inverter circuits is used (For example, see Jinn-Shyan Wang, Yi-Ming Wang, Chin-Hao Chen, Yu-Chia Liu, “An Ultra-Low-Power Fast-Lock-in Small-Jitter All-Digital DLL,” ISSCC 2005/SESSION 22/PLL, DLL, AND VCOs/22.7, 2005 IEEE International Solid-State Circuit Conference, pp. 422-423 and 607).
It is difficult for the inverter chain to provide a signal delay smaller than an inverter delay which is a signal delay of a single inverter circuit included in the inverter chain. Therefore, there is a need for a time adjustment circuit for adjusting the time difference between edges of two input signals with a delay amount smaller than the inverter delay and a time-to-digital converter including the same.